Column redundancy is used in the fabrication of memory devices to improve the overall yield of the fabrication process. If a column, or a number of columns, are found to be defective during the testing of the device, one or more redundant columns can be substituted for the defective columns. The substitution allows the device to function properly despite the defective columns.
Bus-matching features, such as those found in co-pending application U.S. Ser. No. 60/102,035, filed on Sep. 28, 1998, which is hereby incorporated by reference in its entirety, make the implementation of column redundancy much more complex than column redundancy in traditional FIFOs.
Conventional column redundancy circuits, which would require fuses to configure a circuit that multiplexes the data into and out of the faulty memory section to enable the redundant column, do not work with the bus-matching circuit of the co-pending application, since there is not generally a layer of multiplexers to implement such fusing.